1. Field of the Invention
Embodiments of the invention generally relate to semiconductor memory devices, and, more specifically, to low-voltage non-volatile semiconductor memory devices that use an internal voltage at a higher level than a power source voltage.
2. Description of the Related Art
Nowadays, as the operation voltage of semiconductor devices gradually decreases, the degree of integration of the semiconductor devices gradually increases. The decrease of the operation voltage increases the time required to precharge a bit line. As the degree of integration of semiconductor devices increases, the number of memory cells connected to the bit line also increases. This also increases the time required to precharge a bit line. Furthermore, the precharge voltage of the bit line also decreases in proportion to the decrease of the operation voltage, thereby reducing a drain-source voltage of a memory cell. Accordingly, the cell current flowing through the memory cell decreases along with the decrease of the drain-source voltage. This means that the length of time that it takes while the bit line voltage develops increases. As a result, the read time increases as the operation voltage is lowered.